Thesis Defense is here! :)
The Department of Electrical & Electronics Engineering
is pleased to announce the
Oral Defense of the Master’s Thesis of
Ms. Amadea Paula Q. Unisa
Entitled: “Real-time Implementation of Low Bit Rate Wideband Speech Coders on ADSP-21065L”
for the degree of MS in Electrical Engineering
Date: October 14, 2008
Time: 4 pm
Venue: PLDT Multimedia Lecture Hall
Panel Members:
Thesis Adviser: Rowena Cristina L. Guevara, Ph.D.
Chairman: Joel Joseph S. Marciano, Jr., Ph.D.
Members: Luis G. Sison, Ph.D.
Franz A. de Leon, MS EE
Emerson C. Tan, MS EE
This defense is open to the public.
ABSTRACT
In this thesis, real-time Wideband Sinusoidal (WS) and Wideband Linear Prediction (WLP) speech coders were implemented using the ADSP-21065L EZ-Kit LiteTM Evaluation Board. These speech coders are based on the parametric speech models which are extensions of existing sinusoidal and LP models for narrowband speech. The parameters extracted from the input speech are quantized using vector and scalar quantization methods.
A real-time implementation was achieved by programming all the subroutines of the speech coders in assembly language. The average complexities of the WS analysis and synthesis blocks are 1.803 MIPS and 2.95 MIPS. The WS speech coder requires 0.785 kwords of program memory and 5.446 kwords of data memory. For the WLP speech coder, the analysis and synthesis blocks obtained average cycle counts of 28.179 MIPS and 11.249 MIPS. The WLP speech coder occupies 5.98 kwords of program memory and 9.355 kwords of data memory.
Two WS configurations and all of the WLP configurations achieved Mean Opinion Score (MOS) of greater than 3, indicating that the synthesized speech has noticeable but acceptable impairments. All the WS and WLP configurations achieve Diagnotic Rhyme Test (DRT) scores of greater than 80, thus the listener could discriminate between the rhyming pairs of consonant-vowel-consonant (C-V-C) words.
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Hope to see you there 
- dae